In the fields of microelectronics and the microelectromechanical systems (MEMS) the rapid development towards further and further miniaturized devices and higher degree of functionality is limited by packaging and interconnecting capabilities.
A substrate manufactured by the method of the present invention is typically intended for microelectronic devices, electronic MEMS devices, electronic nanotechnology devices, as well as simpler electronic devices. A microelectronic device may comprise microelectronic components such as integrated circuits integrated in, or arranged on, the surface of the substrate. A MEMS device may be formed by micromachining of e.g. a semiconductor substrate or surface micromachining on a substrate.
A fundamental building block in these technology fields is substrates, often referred to as wafers, which typically are made of silicon or other semiconductor materials. Electronic components are formed on, integrated in, or mounted on the surface of such substrates. In addition MEMS components may be formed by micromachining of e.g. a semiconductor substrate or surface micromachining on a substrate. The substrates may be of homogenous material or having different layers and/or regions of different and/or doped material. Typically the substrates are provided with pads and routings for interconnection and mounting. Accompanying the rapid development towards further and further miniaturized devices and higher degree of functionality there is an increasing interest in making electrical via interconnects between opposite sides of a wafer. Hereinafter the electrical via interconnections are interchangeably referred to as via interconnections or simply vias. Using these vias, the conventionally used unreliable, and costly, wire bonding is avoided and components can be more densely packaged.
Numerous via processes and designs have been presented. The strategy for making the vias can be divided into two categories. In the first category the vias are formed by the wafer material, e.g. a doped semiconductor via. In the second category a via hole is formed in the wafer using for example laser ablation, drilling, wet etching or dry etching. Thereafter a conductive material is deposited, e.g. using a physical vapour deposition (PVD) process, on at least the sidewalls of the via hole. To increase the cross sectional area of the via (in order to reduce the electrical resistance) a metal or metal alloy is commonly plated onto the conductive coating. Vias of the first category generally have a relatively high resistance as compared to vias of the second category due to the higher conductivity of the metal or metal alloy. One example of a via interconnection design and a fabrication process that belongs the second category is disclosed in the international patent application WO 2009/005462 A1. This design comprises a via hole having a constriction which provides a high yield, reliable, through-wafer via using processes compatible with conventional processing technologies in the field of microelectronics, MEMS and nanotechnology.
As mentioned above there is an ongoing miniaturisation trend, and thus, as components get smaller, vias has to become arranged more densely arranged in the substrate, and, as pad size becomes smaller, the precision in placement and lateral size of the vias has to be improved. Means for accomplishing this includes formation of high aspect ratio vias. Formation of a high aspect ratio vias of the second category is challenging not least due to the problems related to etching of the via hole and depositing of the conductive material. While being able to form narrow, high aspect ratio, via holes with high precision in placement, such via holes can not readily be provided with a conductive material. Hence an effective diameter of the via hole, i.e. the widest part of the via hole, has to be increased, typically by forming a tapered via hole in order to expose sidewalls of the via hole for deposition of conductive material. This widening limits the precision in placement of vias with respect to a component on the front side of the substrate, since opening of the via hole at the front side has to be carefully controlled.
It is often desirable to form vias extending through layers of different materials and possibly one wants the via to end in a etch stop layer, i.e. the via hole formed should be closed in one end. For example it is often desirable to have a via extending from one side of the substrate to a pad arranged on a plurality of underlying layers made of different materials, such as silicon oxide and silicon nitride, on the other side of the substrate. Etching of the via hole using prior art technologies typically yields an insufficient or uncontrollable etching of the layers of different materials or said underlying layers due to the different etching rates. A similar problem occurs when etching through a substrate and ending in a layer of different material, such as a metal layer arranged on the substrate surface. Then an uncontrolled widening of the via hole at the interface to the layer of different material may occur. In particular, these are problems for high aspect ratio via holes.